1. Field of the Invention
This invention relates to electrical test equipment for semiconductor devices. More specifically, the invention relates to an apparatus and method, which are used to perform dynamic burn-in and full electrical/performance/speed testing on discrete nonpackaged or semi-packaged dies.
2. Background of the Invention
Semiconductor devices are subjected to a series of test procedures in order to assure quality and reliability. This testing procedure conventionally includes xe2x80x9cprobe testingxe2x80x9d, in which individual dies, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level. The electrical connection interfaces with only a single die at a time in wafer; not discrete die.
If the wafer has a yield of functional dies which indicates that quality of the functional dies is likely to be good, each individual die is assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.
The packaged devices are then subjected to another series of tests, which include burn-in and discrete testing. Discrete testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in. Burn-in accelerates failure mechanisms by electrically exercising the devices (DUT) at elevated temperatures, thus eliminating potential failures which would not otherwise be apparent at nominal test conditions.
Variations on these procedures permit devices assembled onto circuit arrangements, such as memory boards, to be burned-in, along with the memory board in order to assure reliability of the circuit, as populated with devices. This closed assembly testing assumes that the devices are discretely packaged in order that it can then be performed more readily.
If the wafer has a yield of grossly functional die, it indicates that a good quantity of die from the wafer are likely to be fully operative. The die are separated with a die saw, and the nonfunctional die are scrapped, while the rest are individually encapsulated in plastic packages or mounted in ceramic packages with one die in each package. After the die are packaged they are rigorously electrically tested. Components which turn out to be nonfunctional, or which operate at questionable specifications, are scrapped or devoted to special uses.
Packaging unusable die, only to scrap them after testing, is a waste of time and materials, and is therefore costly. Given the relatively low profit margins of commodity semiconductor components such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), this practice is uneconomical. However, no thorough and cost effective method of testing an unpackaged die is available which would prevent this unnecessary packaging of nonfunctional and marginally functional die. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions, so that the packaging becomes a limitation for burn-in testing.
It is proposed that multiple integrated circuit devices be packaged as a single unit, known as a multi chip module (MCM). This can be accomplished with or without conventional lead frames. This creates two problems when using conventional test methods. Firstly, discrete testing is more difficult because a conventional lead frame package is not used. Furthermore, when multiple devices are assembled into a single package, the performance of the package is reduced to that of the die with the lowest performance. Therefore, such dies are tested on an individual basis at probe, using ambient and xe2x80x9chot chuckxe2x80x9d test techniques, while still in wafer form. In other words, the ability to presort the individual dice is limited to that obtained through probe testing.
In addition, there is an increased interest in providing parts which are fully characterized prior to packaging. This is desired not only because of the cost of the package, but also because there is demand for multi-chip modules (MCMs), in which multiple parts in die form are tested and assembled into a single unit. While there are various techniques proposed for testing, burning in and characterizing a singulated die, it would be advantageous to be able to xe2x80x9cwafer mapxe2x80x9d the die prior to assembly with as many performance characteristics as possible. Ideally, one would want to be able to map the wafer with full device characterization.
MCMs create a particular need for testing prior to assembly, as contrasted to the economics of testing parts which are discretely packaged as singulated parts. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Even where packaging costs are considerably higher, as in ceramic encapsulated parts, testing unpackaged die is economical for discretely packaged parts when the added costs approximates that of cost of packaging divided by yield:                     C        DIE            xc3x97                        C          PACKAGE                Yield              =                  C        DIE            xc3x97              C                  ADDL          .          KGD                    ⁢              xe2x80x83            ⁢      where                                    C          =          cost                                                          C            DIE                    =                      manufacturing            ⁢                          xe2x80x83                        ⁢            cost            ⁢                          xe2x80x83                        ⁢            of            ⁢                                          xe2x80x83                            ⁢                              xe2x80x83                                      ⁢            functional            ⁢                          xe2x80x83                        ⁢            die                                                                                  C                              ADDL                .                KGD                                      =                          additional              ⁢                              xe2x80x83                            ⁢              cost              ⁢                              xe2x80x83                            ⁢              of              ⁢                              xe2x80x83                            ⁢              testing              ⁢                              xe2x80x83                            ⁢              unpackaged              ⁢                              xe2x80x83                            ⁢              die                                ⁢                      xe2x80x83                                                                    xe2x80x83                    ⁢                      in            ⁢                          xe2x80x83                        ⁢            order            ⁢                          xe2x80x83                        ⁢            to            ⁢                          xe2x80x83                        ⁢            produce            ⁢                          xe2x80x83                        ⁢            known            ⁢                          xe2x80x83                        ⁢            good            ⁢                          xe2x80x83                        ⁢            die            ⁢                          xe2x80x83                        ⁢                          (              KGD              )                                          
Note that in the case of discretely packaged parts, the cost of the die (CDIE) is essentially not a factor. This changes in the case of MCMs:             (              C        DIE            )        xc3x97                  (                  number          ⁢                      xe2x80x83                    ⁢          of          ⁢                      xe2x80x83                    ⁢          die                )            Yield        xc3x97                  C        _            PACKAGE        =            C      DIE        xc3x97          C              ADDL        .        KGD            
Note that again CDIE is not a factor in modules having identical part types; however, the equation must be modified to account for varied costs and yields of die in modules with mixed part types.
With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a x16 memory array module, where probe-to-ship yield of the die is 95%, the costs are:             16      0.95        xc3x97          C      PACKAGE        =      C          ADDL      .      KGD      
so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing an unrepairable module and still be economical. This, of course, is modified by the ability to repair failed modules.
Testing of unpackaged die before packaging into multi-chip modules would be desirable as it would result in reduced material waste, increased profits, and increased throughput. Using only known good die in MCMs would increase MCM yields significantly.
Testing unpackaged die requires a significant amount of handling. Since the test package must be separated from the die, the temporary packaging may be more complicated than either standard discrete packaging or multichip module (MCM) packaging. The package must be compatible with test and burn-in procedures, while securing the die without damaging the die at the bondpads or elsewhere during the process.
In U.S. Pat. No. 4,899,107, commonly assigned, a reusable burn-in/test fixture for discrete TAB die is taught. The fixture consists of two halves, one of which is a die cavity plate for receiving semiconductor dies as the units under test (UUT); and the other half establishes electrical contact with the dies and with a burn-in oven.
The first half of the test fixture contains cavities in which die are inserted circuit side up. The die will rest on a floating platform. The second half has a rigid high temperature rated substrate, on which are mounted probes for each corresponding die pad. Each of a plurality of probes is connected to an electrical trace on the substrate (similar to a P.C. board) so that each die pad of each die is electrically isolated from one another for high speed functional testing purposes. The probe tips are arranged in an array to accommodate eight or sixteen dies.
The two halves of the test fixture are joined so that each pad on each die aligns with a corresponding probe tip. The test fixture is configured to house groups of 8 or 16 die for maximum efficiency of the functional testers.
There are some testing and related procedures when the parts are singulated. For this reason, it is inconvenient to retain multiple die in a single test fixture.
Various forms of connections are used to connect the die to a package or, in the case of a multichip module (MCM), to other connections. These include wirebonding, TAB connections, bump bonding directly to substrate, and conductive adhesives.
The bondpads are conductive areas on the face of the die which are used as an interconnect for connecting the circuitry on the die to the outside world. Normally, conductors are bonded to the bondpads, but it is possible to establish electrical contact through the bondpads by biasing conductors against the bondpads without actual bonding.
One of the problems encountered with burn in and full characterization testing of unpackaged die is the physical stress caused by connection of the bondpads to an external connection circuitry. This problem is complicated by the fact that in many die configurations, the bondpads are recessed below the surface level of a passivation layer. The passivation layer is a layer of low eutectic glass, such as BPSG, which is applied to the die in order to protect circuitry on the die. (The term xe2x80x9ceutecticxe2x80x9d does not, strictly speaking, apply to glass, which is an amorphous fluid; however, the term is used to describe the characteristic of some glasses wherein, as a result of their formulation, they readily flow at a given temperature.)
The ohmic contact between bondpads or test points on a die and a known good die test carrier package has been a matter of interest. It is difficult to achieve and maintain consistent ohmic contact without damaging the bondpads and passivation layer on the die. The design criteria of such contacts is somewhat different from the design criteria of the carrier package.
It has been found desirable to perform testing and related procedures in discrete fixtures prior to final assembly. In order to accomplish this, a reusable burn-in/test fixture for discrete die is provided. The fixture preferably consists of two halves, one of which is a die cavity plate for receiving a semiconductor die as the units under test (UUT).
An intermediate substrate is used to establish ohmic contact with the die at bondpads or testpoints. The intermediate substrate is connected to conductors on the reusable test fixture, so that the bondpads or testpoints are in electrical communication with the conductors on the test fixture.
The intermediate substrate is preferably formed of a semiconductor material, and includes circuitry which is used to conduct signals between bondpad locations and external connector leads on the fixture. The substrate with circuitry is able to establish contact with the external connector leads, or with other leads on the fixture which are in communication with the external connector leads. In the preferred embodiment, the substrate is formed from silicon, although other semiconductor materials may be used. Examples of alternative materials include germanium and silicon on saphire (SOS).
The intermediate substrate includes raised contact members formed in a pattern that matches a corresponding pattern of contact locations on the die (e.g., device bondpads). In an illustrative embodiment the raised contact members are formed using an anisotropic etch process with sloped sidewalls and a flat tip portion. The raised contact members can also be formed using an isotropic etch process.
Each raised contact member includes one or more penetrating projections adapted to penetrate the contact locations on the die and to pierce any residual insulating material to establish a temporary electrical connection. The penetrating projections are formed in a size and shape that permits penetration of the contact location on the die but to a limited penetration depth. For a contact location such as a bond pad, the penetrating projections are formed with a height that is less than a thickness of the bond pad (e.g., {fraction (1/10)} to xc2xe ) to prevent significant damage to the bond pad.
The raised contact members and projections are covered with a conductive layer such as a metal, a silicide or a bi-metal stack. Conductive traces or runners are formed in electrical contact with the conductive layer to establish a conductive path to and from external circuitry (e.g., testing circuitry). The conductive traces can surround or enclose the base of the contact members to ensure an efficient electrical connection between the traces and the conductive layer.
Preferably a large number of intermediate substrates are formed on a single wafer using fabrication techniques used in semiconductor manufacture. The wafer can then be diced (e.g., saw cut) to singulate the intermediate substrates.
In a modification of the invention, a Z-axis anisotropic conductive interconnect material is provided as an interface between the substrate and the die. The Z-axis anisotropic conductive interconnect material is used to establish ohmic contact with bondpads or the equivalent attach points on the semiconductor die. The Z-axis anisotropic conductive interconnect material is able to conform to the shape of the die at the bondpad sufficiently to establish the ohmic contact without substantially damaging the bondpad. Since contact is able to be established by biasing force, it is possible to perform burn in and test of the die without resorting to bonding a conductor to the bondpad.
The Z-axis anisotropic conductive interconnect material is a metal filled polymer composite which is able to function as a compliant interconnection material for connector and testing applications. This material is in a group of materials which are referred to as elastomeric conductive polymer interconnect (ECPI) materials. These are available from ATandT Bell Laboratories, of Allentown, Penn., or Shin Etsu Polymer America Inc., of Union City, Calif., 3M Company of Minneapolis, Minn., at their Austin, Tex. plant or Nitto Denko America, Inc., San Jose, Calif. (a subsidiary of Nitto Denko Corporation of Japan).
The contact between the bondpads and the external connector leads is therefore established by utilizing the Z-axis anisotropic conductive interconnect material and substrate with circuitry. Conductors on the Z-axis anisotropic conductive interconnect material and substrate with circuitry extend from the bondpads to connection points, and the connection points conduct to contacts, which are in turn in communication with the external connector leads. The self-limiting nature of the bump is transferred through the Z-axis anisotropic conductive interconnect material so that the potential damage to the bondpad by force exerted through the Z-axis anisotropic conductive interconnect material is limited.
In a preferred embodiment, the intermediate substrate is placed in the die receiving cavity and is electrically connected to conductors on the fixture, which in turn are connected to the connector pins. The die is placed face down in the die receiving cavity. The substrate is attached to conductors on the fixture, which in turn are connected to the connector pins. Ohmic contact is established between bondpads or testpoints on the die and conductors on the substrate.
Z-axis anisotropic conductive interconnect material may be placed in the die receiving cavity beneath the die so that the ohmic contact with the bondpads or testpoints on the die may be established through the Z-axis anisotropic conductive interconnect material, through the substrate, to communicate with external connector leads on the fixture.
In an alternate embodiment, a die is placed face up in a cavity in a first half of the fixture, and the semiconductor substrate is placed over the die. In the preferred form of that embodiment, the external connector leads are connector pins, which preferably are in a DIP (dual inline package) or QFP (quad flat pack) configuration. The pins terminate at the connection points.
The fixture establishes electrical contact with the a single die and with a burn-in oven, as well as permitting testing of dies in discretely packaged form.
If the die is placed face up in a cavity in a first half of the fixture, the substrate may be placed between the die and a lid. Attachment of the die to the external connection leads is established either through contact points on the substrate, or through the contact points through the Z-axis anisotropic conductive interconnect material, in which case, the substrate establishes contact with the Z-axis anisotropic conductive interconnect material.